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PCell Design Principles for Advanced Nodes

The primary responsibility of a PCell is not to generate layout quickly, but to prevent invalid layout from ever being created.

What Should Be Forbidden at the PCell Level

• Continuous transistor width
• Arbitrary gate length selection
• User-controlled gate cut placement
• Single-fin devices in product mode
• Fin pitch modification
• Arbitrary fin termination near active edges
• Free contact or via placement

Why Forbid Instead of Fix

OPC and DRC are verification tools. They are not design tools.

If a structure must be corrected by OPC, it should not be generated by default.

PCM vs Product Separation

Exploration and production require different freedoms.

if pcmMode: allow exploration else: strictly enforce rules

Guiding Principle

A good PCell does not make designers smarter. It makes bad designs impossible.

This principle scales teams, technologies, and manufacturing outcomes.

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