Case Studies
A collection of practical case studies covering semiconductor, automation, and applied engineering topics.
These case studies are grounded in a broader perspective on EDA sign-off, manufacturing readiness, and system-level verification.
Background, experience, and verification philosophy
Read AboutHow sign-off tools fit into the RTL-to-GDS flow
View ComparisonReal-world applications and execution examples
Topology-Driven TVS Reliability & Latch-Up Prevention
Combining PERC LDL structural verification with laboratory TVS characterization to eliminate cross-domain latch-up risk.
FEATURED · AI CASE STUDY AI Systems Feb 7, 2026Production-Grade AI in Semiconductor Manufacturing
Deploying AI as a production-grade system in a high-risk semiconductor manufacturing environment, with MLOps as the central control layer.
FEATURED · 3D-IC CASE STUDY Semiconductor Dec 31, 20253D IC Chiplet-Based AI NPU Architecture
Advanced chiplet-based packaging approach for scalable, high-performance AI processor architectures.
CASE STUDY Automation Dec 30, 2025Automation Application Engineering
Customer-focused automation system deployment and application-driven engineering support.
FEATURED · PACKAGE CASE STUDY Semiconductor Feb 1, 2026Advanced IC Package Implementation and Verification
Structured package design and verification workflows for chiplet and 3D IC technologies.
CASE STUDY Semiconductor Feb 2, 2026Practical ERC for Foundry, Safety, and Reliability
A whitepaper-style case study explaining how Electrical Rule Checking (ERC) encodes design intent, voltage awareness, and safety constraints beyond traditional DRC and LVS.
CASE STUDY Semiconductor Feb 3, 2026Ensuring IP Integrity Across Complex SoC Designs
Preventing silent IP corruption through early and sign-off verification.
CASE STUDY Semiconductor Feb 3, 2026Accelerating LVS Closure with V2LVS
Reducing LVS debug cycles through layout-aware verification.
CASE STUDY Semiconductor Feb 3, 2026Eliminating Latch-up Risk with Automated Guard Ring Verification
Applying ESDA-compliant PERC checks to improve silicon reliability.
CASE STUDY Semiconductor Feb 3, 2026Predictable High-Level Synthesis Verification
Ensuring C++ and SystemC design intent integrity from algorithm to RTL.
CASE STUDY Semiconductor Feb 3, 2026AI-Native Place-and-Route PPA Closure
Replacing manual P&R tuning with AI-driven implementation strategies.
CASE STUDY Semiconductor Feb 3, 2026AI-Driven RTL-to-GDS Digital Implementation
Transforming RTL-to-GDS closure using generative and agentic AI.
CASE STUDY Semiconductor Feb 3, 2026High-Bandwidth Memory Bus Delay Optimization
Automating signal alignment for next-generation HBM designs.
CASE STUDY Methodology Feb 3, 2026Shifting Sign-off Verification Left
Reducing tape-out risk by introducing sign-off verification earlier.
CASE STUDY Automation Feb 3, 2026Data-Driven Manufacturing with Industrial IoT
Unifying asset and process data for scalable operations.
CASE STUDY Automation Feb 3, 2026Manufacturing Readiness with Digital Twins
Reducing production risk through virtual process validation.
FEATURED · FOUNDRY CASE STUDY Manufacturing Feb 3, 2026ML-Assisted OPC Hotspot Verification
Reducing lithography risk and improving yield confidence through machine learning–based hotspot classification.
FEATURED · DFM TECH NOTE Semiconductor Feb 28, 2026Calibre DFM PVR Automation Framework
Bridging Calibre PVR analysis and automated layout correction through rule-based IR-drop and reliability enhancement scripting.