Industrial Technical Note – Prototype Stage 1
In advanced semiconductor nodes, power integrity and reliability verification are mandatory signoff requirements. Calibre DFM / PVR tools detect:
The bottleneck exists between RDB output and Layout Fix. This automation addresses that gap.
This mirrors industrial automation structure:
The script performs:
[
{
"id": 1,
"coordinate": [120.5, 450.2],
"drop_mv": 45,
"type": "IR_DROP",
"net": "VDD"
},
{
"id": 4,
"coordinate": [150.2, 300.5],
"drop_mv": 0,
"type": "SINGLE_VIA",
"net": "SIGNAL_A"
}
]
if entry["type"] == "IR_DROP" and entry["drop_mv"] > threshold:
→ Generate WIDEN_METAL action
if entry["type"] == "SINGLE_VIA":
→ Generate ADD_REDUNDANT_VIA action
[
{
"action": "WIDEN_METAL",
"target_net": "VDD",
"coord": [120.5, 450.2]
},
{
"action": "ADD_REDUNDANT_VIA",
"target_net": "SIGNAL_A",
"coord": [150.2, 300.5]
}
]
# IR drop 45mV > 40mV db_enhance_metal -net VDD -coord 120.5 450.2 -add_width 0.2 # IR drop 85mV > 40mV db_enhance_metal -net VDD -coord 500.0 500.0 -add_width 0.2 # Single Via Reliability db_insert_via -net SIGNAL_A -coord 150.2 300.5 -type DOUBLE
Reduces manual review workload in large SoC environments.
Future rules can include EM, density, CMP, or advanced power grid optimization.