Bringing Predictability and Verification Confidence to High-Level Synthesis Design Flows
Ensuring C++/SystemC Design Intent Integrity from Algorithm to RTL
Improved confidence and predictability in High-Level Synthesis flows by introducing formal, coverage-driven verification from C++/SystemC to RTL. This approach reduced late-stage debug, ensured design intent preservation, and enabled production-quality hardware results from HLS methodologies.
Applied using the Pavix execution framework
Context
High-Level Synthesis (HLS) allows hardware designers to describe design intent at higher abstraction levels using C++ or SystemC, enabling faster architecture exploration and RTL generation.
While HLS significantly accelerates development, many teams struggle to achieve production-quality results due to verification challenges and uncertainty around equivalence between high-level models and generated RTL.
The Challenge
In traditional HLS flows, verification often becomes disconnected from the original C++/SystemC source.
- Difficulty correlating RTL errors back to high-level source code
- Limited confidence that generated RTL truly matches golden C++ intent
- Misleading results from software-oriented C++ coverage tools
- Late discovery of functional mismatches during downstream RTL verification
These gaps reduce trust in HLS and force teams to rely on manual debug and rework.
Why Traditional Approaches Fall Short
Conventional verification methodologies were designed for hand-written RTL and provide limited visibility into the semantics of high-level algorithmic code.
Software-based C++ coverage tools lack awareness of hardware constructs such as concurrency, state, and signal activity, leading to inaccurate coverage assessment and poor linkage to downstream RTL verification.
Solution Approach
A comprehensive High-Level Verification (HLV) strategy was introduced to verify and clean C++/SystemC designs before synthesis and formally prove equivalence between high-level code and generated RTL.
This approach integrated formal equivalence checking and hardware-aware coverage directly into the HLS flow.
Technical Execution
- Early verification and cleanup of C++/SystemC source code
- Formal equivalence checking between golden C++ and generated RTL
- Hardware-aware code coverage applied at the C++ level
- Linking high-level coverage results to RTL verification databases
- Clear traceability from algorithm intent to final RTL implementation
This methodology ensured that functional correctness and coverage closure were addressed at the appropriate abstraction level.
Results & Impact
- Earlier detection of functional and structural issues
- Reduced downstream RTL debug and re-verification effort
- Higher confidence in HLS-generated RTL quality
- Improved collaboration between algorithm, architecture, and RTL teams
- Production-ready HLS adoption with predictable outcomes
Key Takeaway
High-Level Synthesis does not eliminate the need for rigorous hardware verification. By integrating formal equivalence and hardware-aware coverage into the HLS flow, teams can achieve both productivity gains and production-level confidence.