Engineering judgment, evolved through automation and AI-assisted workflows.
Seasoned semiconductor professional with 30 years of experience across EMEA and APAC, spanning advanced IC design, Physical design, EDA physical verification OPC / RET, and design-to-mask flows.
Proven expertise in complex, high-value B2B engagements, combining deep, sign-off-level technical credibility with strong commercial leadership and extensive APAC sales experience.
Demonstrated ability to align customer business priorities with advanced semiconductor and EDA solutions, bridging design, verification, and manufacturing readiness.
Recognized for close collaboration with senior management, engineering teams, and leading global foundries to mitigate risk, enable successful tape-outs, and drive sustained revenue growth across safety- critical and automotive programs.
Below 14nm, layout design is no longer about drawing shapes. It is about constraining degrees of freedom to ensure manufacturability, yield, and predictable OPC convergence.
This section documents my work and thinking around FinFET PCell architecture, DFM- and OPC-aware layout automation, and testchip / PCM methodology.
How layout thinking must change below 14nm: from geometry-driven design to topology- and constraint-driven architecture.
Read overview →Why planar MOS PCell concepts fail in advanced nodes and how FinFET PCell architecture must be structured.
Explore FinFET PCell architecture →Analysis of the most difficult OPC interactions in FinFET layouts and how PCell-level constraints reduce risk.
Read OPC analysis →What must be forbidden at the PCell level in advanced nodes to ensure manufacturability, yield stability, and OPC convergence.
Read PCell design principles →End-to-end responsibility for physical verification and tape-out readiness.
View highlight →Scalable automation improving verification predictability and turnaround time.
View highlight →STAR-based technical discussion guide mapped to real projects.
View guide →My current and future-facing technical focus areas. These tracks represent how I actively evolve my engineering practice beyond traditional domain boundaries.
Python as a core problem-solving language for data analysis, automation, and structured experimentation.
Explore Python track →AI-assisted engineering focused on reasoning, prompt design, and workflow augmentation using Claude.
Explore AI track →Structured access to career progression, professional documents, and in-depth technical portfolios. Each category is designed for continuous expansion.
Professional timeline highlighting role evolution, technical depth, and leadership across semiconductor, EDA, and manufacturing domains.
View career timeline (PDF) →Deep-dive portfolios covering physical verification, sign-off ownership, automation, and methodology development.
Explore EDA portfolio →Customer-facing engineering and technical sales experience enabling successful ASIC adoption from evaluation through tape-out.
Explore sales & customer application success →Selected case studies highlighting practical engineering experience and real-world problem solving.
Advanced chiplet-based packaging for scalable AI systems.
CASE STUDY Automation Feb 14 2025Customer-focused automation system deployment and application-driven engineering support.
CASE STUDY Semiconductor Feb 13 2026A whitepaper-style case study explaining how Electrical Rule Checking (ERC) captures design intent, voltage awareness, and safety constraints beyond traditional DRC and LVS.