Practical ERC for Foundry, Safety, and Reliability

Electrical Rule Checking (ERC) as a design-intent and reliability verification methodology beyond traditional DRC and LVS.

Introduction

Electrical Rule Checking (ERC) complements DRC and LVS by focusing on electrical correctness, voltage intent, and reliability risks. This case study consolidates practical ERC usage together with foundry- and safety-oriented concepts commonly applied in real semiconductor projects.

1. Practical ERC Checks (Design-Level)

This section covers fundamental ERC checks that detect common but critical design issues early in the development cycle.

Floating Gate / Floating Net

Detects MOS gates or nets that are not driven. Floating gates can cause unpredictable behavior, especially in analog, sensor, and automotive ICs. 


ERC FLOATING_GATE
  DEVICE MOS
  TERMINAL GATE
  CONDITION NOT CONNECTED
END

VDD–VSS Short

Detects shorts between power and ground that may not be caught by LVS alone.

Multiple Driver on a Net

Identifies nets driven by multiple outputs, preventing contention and long-term reliability issues.

Well Tie and Bulk Connection

Ensures proper NWELL/PWELL and bulk connections to prevent latch-up and leakage issues.

2. Foundry-Style ERC (GlobalFoundries Perspective)

Foundry-style ERC encodes manufacturing, voltage, and reliability intent directly into rule decks.

Voltage Domain Crossing

ERC rules enforce the presence of level shifters between voltage domains to avoid gate-oxide stress.

Over-Voltage Device Protection

Checks correct usage of high-voltage and low-voltage devices across different voltage domains.

Power Sequencing and Back-Powering

Detects unsafe power-up sequences that may cause unintended current paths, especially critical for automotive ECUs.

Safety-Critical Signal Integrity

Ensures that safety-related signals are never floating or multiply driven.

ESD Protection Path Verification

Verifies that all IO pads have valid ESD discharge paths.

Conclusion

Effective ERC is not a checkbox exercise but a way to encode design intent and reliability requirements into verification flows. When used correctly, ERC significantly reduces late-stage failures and improves sign-off confidence.