Engineering practice across EDA, automation, and AI-assisted workflows

Domain Overview (EDA & Manufacturing Foundations)

TechNotesPark is my personal technical workspace documenting how long-standing semiconductor and EDA experience evolves through modern automation, data-driven analysis, and AI-assisted engineering workflows.

This site intentionally combines two dimensions: deep, production-grade EDA and manufacturing sign-off expertise, and continuous evolution through Python-based automation and AI-assisted reasoning.

How to Read This Site

The sections below preserve detailed, domain-specific knowledge accumulated across advanced-node programs, sign-off ownership, and foundry-facing engagements. These foundations are complemented by newer tracks focused on scalability, automation, and reasoning augmentation.

Engineering Foundations & Detailed Domain Work

About TechNotesPark

Semiconductor Physical Verification & Manufacturing Readiness Portfolio

Overview

TechNotesPark is a personal technical portfolio covering physical verification, EDA sign-off methodologies, and design-to-manufacturing workflows across advanced ASIC and foundry programs.

In advanced technology nodes (12nm and below), my focus extends beyond verification execution to layout architecture and methodology design. This includes defining which layout freedoms must be exposed, and more importantly, which must be forbidden to ensure manufacturability, yield, and OPC convergence.

From Sign-off Expertise to Scalable Methodology

In advanced technology nodes, layout quality is no longer determined by geometry alone, but by how effectively design freedom is constrained. My work emphasizes layout architecture and methodology design—defining which degrees of freedom must be exposed, and which must be deliberately forbidden—to ensure manufacturability, yield stability, and predictable OPC convergence.

This perspective naturally extends into automation. Rather than relying on downstream sign-off correction, engineering judgment is encoded directly into PCell architectures, rule-aware flows, and repeatable verification frameworks.

Why Python and AI

Python serves as a practical bridge between engineering intuition and scalable execution. It enables rapid automation, structured data exploration, and reproducible analysis grounded in real EDA problems.

In parallel, my AI and Claude Code explorations focus on augmenting engineering reasoning—using large language models to clarify intent, explore alternatives, and accelerate iteration without replacing human judgment.

Together, Python and AI extend my existing practice by formalizing experience into workflows and amplifying structured thinking in complex, constraint-driven engineering environments.

A key part of this work is the design of PCell architectures for planar and FinFET technologies, where topology, technology rules, and DFM constraints are encoded directly into automation flows.

My Role & Background

I am a senior semiconductor professional with over 29 years of experience spanning physical verification, sign-off ownership, and design-to-manufacturing enablement across EMEA and APAC.

My work has focused on foundry-facing verification methodologies, including DRC, LVS, PERC, RET, and manufacturing readiness at advanced and legacy nodes.

I have supported complex ASIC and packaging programs by bridging EDA technology, customer design challenges, and business objectives, while leading high-value B2B engagements with engineering and executive stakeholders.

More recently, my work has emphasized advanced-node layout methodology, particularly the transition from geometry-driven design to constraint- and topology-driven architectures. This shift is essential for scaling layout quality across FinFET-based nodes where OPC freedom is limited and manufacturing variability is amplified.

Design Philosophy

Design tools create layouts.
Sign-off tools decide manufacturability.

In advanced nodes, this philosophy extends one step further: manufacturability must be designed before sign-off. Well-architected PCells and layout automation should prevent invalid structures from being created at all, rather than relying on downstream fixes.

Advanced-Node Layout Architecture

Below 14nm, layout challenges are dominated not by rule complexity, but by interacting constraints across lithography, process variability, and limited OPC correction capability.

My approach to advanced-node layout architecture focuses on:

• Eliminating non-physical degrees of freedom (e.g. continuous width in FinFETs)
• Encoding DFM and OPC constraints directly at the PCell level
• Separating exploration (PCM) from production-ready design rules
• Designing layout automation that scales across teams and technologies

This architectural perspective complements traditional sign-off expertise by shifting risk mitigation earlier in the design flow.

EDA Sign-off Landscape

The table below summarizes the positioning of major EDA vendors in digital implementation and sign-off.