Calibre PERC LDL DRC Flow – Key Capabilities & Value

1. Execution & Command-Line Capability

Enables topology-aware DRC integrated with layout verification in a hierarchical and scalable environment.

Topology-aware DRC in hierarchical mode
Multi-threading and hyperscaling support
Integrated LVS + PERC + LDL flow
Incremental LDL execution for faster rule development
Source-based flow for schematic-to-layout mapping

2. Results Data Management & Revision Control

DFM Database-based storage allows checkpointing, revision control, and structured debugging.

Export to RDB / GDS / OASIS formats
Revision freeze and checkpoint management
Incremental verification workflows
Interactive debugging through Calibre RVE

3. DRC Result Waiver Management

Automated waiver handling improves repetitive error management and sign-off stability.

Auto-waiver support
Waiver setup file integration
Unused waiver tracking
Automated waiver statistics reporting

4. Edge Collection & Non-Simple Polygon Checking

Ensures geometric integrity and detects self-intersecting polygons.

Automatic non-simple polygon detection
Optional coordinate-check optimization
DFM database-based geometry control

5. Point-to-Point Resistance (P2P) Analysis

Layout-based resistance extraction for ESD, latch-up, and bulk resistance validation.

Gate bulk pin resistance comparison
Cross-domain resistance validation
ESD discharge path resistance analysis
Topology-based resistance imbalance detection

6. Source-Based LDL Flow

Simulation-context-aware verification through schematic-to-layout object mapping.

Source-to-layout object correlation
Simulation-aware DRC checks
Hierarchical cell mapping control
LVS-based object correspondence usage

Core Value of LDL DRC

Detects topology-based issues not visible in traditional DRC
Validates ESD, latch-up, and resistance mismatch risks
Unifies layout, circuit topology, voltage, and resistance verification
Scalable rule automation platform for large SoC designs

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