Calibre-based OPC Flow (Production Perspective)

This document describes the actual production OPC flow used in Siemens EDA Calibre, reflecting industry-standard practices for advanced semiconductor manufacturing.

1. Overall OPC Flow Diagram

[GDS Layout]
     |
     v
[Design Preparation / Fracturing]
     |
     v
[Rule-based OPC]
(Coarse bias, serif, hammerhead)
     |
     v
[Model-based OPC]
(Lithography simulation & edge correction)
     |
     v
[ILT (Optional / Hotspots only)]
(Global optimization)
     |
     v
[OPC Verification / Sign-off]
(Process window, PV band)
     |
     v
[Mask Data Preparation (MDP)]
     |
     v
[Tape-out]

The Calibre OPC flow is inherently hierarchical:
speed is achieved through rule-based OPC,
while accuracy is achieved through model-based OPC and selective ILT.

2. Input Layout: GDS

Standard cells
Memory arrays
Custom logic blocks

At this stage, no lithography effects are considered. The layout represents the ideal target geometry.

3. Design Preparation / Fracturing

The layout polygons are converted into an edge-based representation that can be manipulated by the OPC engine.

Polygon-to-edge decomposition
Segment length control
Corner classification

Key concept: OPC operates on edges, not polygons.

4. Rule-based OPC (Coarse Correction)

Rule-based OPC applies predefined geometric corrections based on pattern type and local context.

Line biasing
Hammerhead insertion
Serif generation
Simple SRAF placement

Characteristic	Description
Speed	Very fast
Accuracy	Limited
Prediction	No wafer simulation

Goal: Remove large systematic lithographic errors early.

5. Model-based OPC (Core Step)

Model-based OPC uses calibrated lithography models to predict wafer contours and iteratively correct mask edges.

Mask
 ↓
Optical Model (Hopkins)
 ↓
Aerial Image
 ↓
Resist Model (Mack)
 ↓
Wafer Contour
 ↓
Error to Target
 ↓
Edge Adjustment (Iterative)

Physics-based prediction
High CD accuracy
Computationally expensive

This step determines the final pattern fidelity on silicon.

6. ILT – Inverse Lithography Technology (Optional)

ILT is selectively applied to critical hotspots where conventional OPC cannot meet process window requirements.

Global optimization approach
Pixel- or level-set-based mask representation
Very high computational cost

ILT is not applied to full-chip layouts in production.

7. OPC Verification and Sign-off

The OPC-corrected mask is verified using full lithography simulation.

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