Why ASML and TSMC Use Partial ILT

Inverse Lithography Technology (ILT) provides the highest pattern fidelity in computational lithography. However, despite its theoretical advantages, full-chip ILT is not used in high-volume manufacturing. This document explains why industry leaders such as ASML and TSMC adopt partial ILT instead.

1. What ILT Really Is

ILT formulates mask synthesis as a global optimization problem:

Minimize wafer contour error
while enforcing mask manufacturability

Unlike traditional OPC, ILT does not rely on local edge corrections. Instead, it computes the optimal mask shape that best reproduces the target wafer pattern.

ILT provides the best possible lithographic solution — at a very high cost.

2. What “Partial ILT” Means in Production

Partial ILT refers to the selective application of ILT only to critical lithography hotspots, rather than to the entire chip.

Rule-based OPC   → Full chip
Model-based OPC  → Full chip
ILT              → Selected hotspots only

Typically, hotspot regions represent less than 1% of the total layout area.

3. Why ASML and TSMC Use Partial ILT

3.1 Computational Cost Explosion

ILT uses pixel- or level-set-based mask representations, which dramatically increase the number of optimization variables.

Full-chip ILT runtime: weeks to months
Hotspot ILT runtime: hours to days

From a return-on-investment perspective, applying ILT only where it matters provides maximum benefit at minimal cost.

3.2 Mask Write and Inspection Limitations

ILT masks tend to be:

Highly curvilinear
Extremely fragmented
Dense with sub-resolution features

This results in:

Excessive mask write time
Increased mask cost
Difficult inspection and repair

Mask shops cannot reliably support full-chip ILT masks at production scale.

3.3 Diminishing Returns Compared to Model-based OPC

For the majority of layout patterns, well-calibrated model-based OPC already meets CD and process window requirements.

ILT provides significant improvement only for:

Complex 2D patterns
Forbidden pitch regions
Severe process window limiters

Applying ILT everywhere yields little additional benefit while dramatically increasing cost.

3.4 Process Window Optimization Strategy

ILT is most effective when used to recover process window in the most lithographically sensitive regions.

Since process window margin is not uniformly required across the chip, selective ILT is the most efficient strategy.

4. Why ILT Is Not Fully Used in Production

Limitation	Impact on Production
Runtime	Violates tape-out schedules
Mask manufacturability	High risk of mask write failure
Inspection & repair	Yield and reliability risk
Cost vs. benefit	Economically unjustifiable

5. ASML vs. TSMC Perspective

ASML (Tool and Platform Provider)

Focus on extending lithographic limits
Develops full ILT and curvilinear mask solutions
Research-driven approach

TSMC (High-Volume Manufacturer)

Focus on throughput and yield stability
Cost-sensitive decision making
Production-driven approach

ASML asks: “Is it physically possible?”

TSMC asks: “Can we manufacture it reliably at scale?”

6. Production-Proven Strategy

Most layout patterns      → Model-based OPC
Difficult hotspots        → Partial ILT
Extreme cases             → Layout re-design

7. I-ready Summary

Although ILT delivers superior pattern fidelity, its computational cost and mask manufacturability challenges prevent full-chip deployment. Therefore, companies like ASML and TSMC use partial ILT, applying it selectively to lithography hotspots where conventional OPC cannot meet process window requirements.

8. Final Takeaway

ILT is the most powerful computational lithography technique
Full-chip ILT is impractical for high-volume manufacturing
Partial ILT offers the best balance between accuracy and cost

Partial ILT is not a compromise — it is an optimized production strategy.

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